This invention relates to an active matrix display apparatus, and more particularly to improvements in or relating to a display apparatus that adopts a “plural pixel simultaneous sampling method” of writing a video signal at a time into a plurality of pixels.
FIG. 4 shows a typical example of a conventional active matrix display apparatus. Referring to FIG. 4, the display apparatus 0 shown includes a pixel array section 9, a horizontal drive circuit 6, a pair of vertical drive circuits 4, and a precharge drive circuit 8. The pixel array section 9 includes gate lines 1 extending in the direction of a row, signal lines 2 extending in the direction of a column, and pixels 3 disposed at points at which the gate lines 1 and the signal lines 2 intersect with each other. The vertical drive circuits 4 are disposed in a leftward and rightward separated relationship from each other and line-sequentially drive the gate lines 1 from the opposite sides to successively select the pixels 3 in a unit of a row. The horizontal drive circuit 6 is connected to the signal lines 2 and samples a video signal supplied thereto from the outside to the signal lines 2 thereby to write the video signal into the selected row of the pixels 3. In this instance, usually “dot sequential driving” of successively writing the video signal into the individual pixels is used. Also the precharge drive circuit 8 is connected to the signal lines 2. Where the dot sequential driving is used and the video signal to be written into the pixels is inverted for each one row, if charging/discharging current upon sampling of the video signal to the signal line 2 provided for each column of the pixel array section 9 is high, then this appears as a “vertical stripe” on the display screen. In order to suppress the charging/discharging current upon sampling of a video signal as low as possible, a precharge signal supplied through a precharge line is applied to the signal lines 2 in the precharge drive circuit 8 prior to dot sequential writing of a video signal. The precharging is performed prior to dot sequential writing of a video signal into the pixels 3 and samples the precharge signal to the signal lines 2 similarly in a dot-sequential fashion.
In an active matrix display apparatus which adopts the dot sequential driving scheme, in order to raise the resolution of a panel, the number of pixels is increased. As a result of increase of the number of pixels, if the dot sequential driving is performed one by one pixel, then the writing time of a video signal to be allocated to one pixel becomes short. In order to cope with this, a plurality of video lines are provided in the panel to input a plurality of video signals, and the video signals are sampled at a time to a plurality of pixels to obtain a sufficient writing period of time. In this instance, it is necessary to adjust the phases of the plurality of systems of video signals relative to one another in advance. According to the conventional standards (XGA, SXGA) for an active matrix display apparatus, the simultaneous sample number is 12. However, as the rise of the resolution of pixels further proceeds, it becomes impossible to assure a sufficient writing period of time with the simultaneous sample number of 12. For example, the UXGA standards adopt simultaneous sampling of 24 pixels. A layout of video lines in this instance is shown in FIG. 5.
Referring to FIG. 5, the display apparatus shown includes a pixel array section which in turn includes gate lines 1 extending in the direction of a row, signal lines 2 extending in the direction of a column, and pixels 3 disposed in rows and columns at points at which the gate lines 1 and the signal lines 2 intersect with each other. In the arrangement shown in FIG. 5, each of the pixels 3 is formed from a thin film transistor (TFT) and a liquid crystal cell LC. The gate electrode of the thin film transistor TFT is connected to the corresponding gate line 1, and the source electrode is connected to the corresponding signal line 2 while the drain electrode is connected to one of electrodes (pixel electrode) of the corresponding liquid crystal cell LC. A predetermined counter potential is applied to the other electrode (counter electrode) of the liquid crystal cell LC. The vertical drive circuit 4 is connected to the gate lines 1 and sequentially select the rows of the pixels 3. The panel includes 24 video lines SIG1 to SIG24 laid thereon, and 24 systems of video signals are supplied in a predetermined phase relationship to the panel. In the arrangement shown in FIG. 5, the 24 video lines SIG1 to SIG24 are laid between the pixel array section and the horizontal drive circuit 6. A sampling switch set is disposed between the flux of the horizontal lines SIG1 to SIG24 and the signal lines in the columns. The sampling switch set includes units of 24 switches HSW connected between units of 24 signal lines and the 24 video lines SIG1 to SIG24. The horizontal drive circuit 6 includes a shift register having multiple stages and operates in response to a clock signal HCK supplied thereto from the outside to successively transfer a start pulse HST supplied thereto from the outside similarly to successively output drive pulses A, B, . . . from the successive stages of the shift register. The horizontal drive circuit 6 drives 24 switches HSW at a time with each one of the drive pulses to sample the 24 systems of video signals SIG1 to SIG24 to the corresponding 24 signal lines 2. The horizontal drive circuit 6 performs such sampling successively for the different sets of 24 signal lines 2 and writes the video signals SIG1 to SIG24 into the pixels 3 of the selected row. In the following description, a video signal and a video line may be referred to with a same reference character SIG (SIG1 to SIG24).
A precharge line PSIG is laid between the pixel array section and the precharge drive circuit 8 shown below the pixel array section in FIG. 5 and supplies a precharge signal PSIG of a predetermined level from the outside. Also the precharge line and the precharge signal may be referred to with a same reference character. Another sampling switch set is disposed between the single precharge line PSIG and the signal lines 2 extending in the columns. Similarly to the switches HSW for writing video signals, the switches PSW for writing a precharge signal are driven to open or close in a unit of 24 switches HSW by the precharge drive circuit 8. Accordingly, the precharge drive circuit 8 has a configuration similar to that of the horizontal drive circuit 6 and includes a shift register having multiple stages. The shift register operates in response to a clock signal PCK supplied thereto from the outside and successively transfers a precharge start pulse PST supplied thereto from the outside similarly to successively outputs drive pulses A′, B′, . . . .
FIG. 6 illustrates operation of the display apparatus shown in FIG. 5. Referring to FIG. 6, the precharge start pulse PST is inputted first, and then the horizontal start pulse HST is inputted consecutively. Further, the operation clock signal HCK supplied to the horizontal drive circuit 6 and the precharge operation clock signal PCK supplied to the precharge drive circuit 8 have a pulse train of an equal frequency. The precharge drive circuit 8 transfers the precharge start pulse PST in response to the precharge operation clock signal PCK to successively output the drive pulses A′, B′, C′, . . . for the switches PSW. Consequently, 24 switches PSW in each set are driven simultaneously to successively write a precharge signal into the corresponding signal lines 2. Concurrently, the horizontal drive circuit 6 operates in response to the operation clock signal HCK to successively transfer the horizontal start pulse HST to successively output the drive pulses A, B, C, . . . for the switches HSW. Consequently, the video signals are successively sampled in a unit of 24 signal lines 2. Since the precharge start pulse PST precedes to the horizontal start pulse HST, sampling of the precharge signal is performed preceding to the sampling of the video signals.
A subject to be solved by the present invention is described below with reference back to FIG. 5. Generally, a parasitic capacitance appears between intersecting wiring lines in a panel. Particularly where the simultaneous sampling method is used, each of the 24 video liens SIG1 to SIG24 extends in an intersecting relationship with the signal lines 2, and the capacitance at each of the intersecting portions is applied as a parasitic capacitance to each of the video lines SIG1 to SIG24. As the parasitic capacitance of each video line increases, the video signal SIG becomes blunt, which makes a cause of a display defect called ghost. If the simultaneous sample number is doubled, then also the parasitic capacitance is doubled, and such blunt deformation of a video signal pulse as described above becomes worse and the ghost margin decreases. Particularly where the dot line inverse driving method is used, the polarities of video signals supplied to adjacent video lines are opposite to each other. Therefore, the capacitance value felt by each video line further increases and the ghost margin is further deteriorated, and this is a subject to be solved.